1. Field of the Invention
The present invention relates to a display driving method and a display driving circuit and more particularly to the display driving method and the display driving circuit for a display such as a liquid crystal panel and an electroluminescence panel (EL panel).
The present application claims the Convention Priority of Japanese Patent Application No. Hei11-316872 filed on Nov. 8, 1999 Hei11-316872 filed on Nov. 8, 1999, which is hereby incorporated by reference.
2. Description of the Related Art
FIG. 7 is a block diagram showing an electric configuration example of a conventional liquid crystal panel 1 and a display driving circuit disclosed in Japanese Patent Application Laid-open No. Hei11-143432.
The liquid crystal panel 1 is an active matrix driving liquid crystal panel using a thin film transistor (TFT) used as a switch element. Intersection points of n-pieces (n is a positive integer) of scanning electrode 21 to scanning electrode 2n (gate line) provided at predetermined intervals in a row direction and m-pieces (m is a positive integer) of data electrode 31 to data electrode 3m (source line) provided at predetermined intervals in a column direction are used as pixels. For each pixel, a liquid crystal cell 4 which is an equivalent capacitive load, a TFT 5 for driving a corresponding liquid crystal cell 4 and a capacitor 6 for storing data charges for one vertical synchronous period are arranged. A data red signal, a data green signal and a data blue signal generated based on a red data DR, a green data DG and a blue data DB to be digital image data are sequentially applied to data electrode 31 to data electrode 3m and scanning signals are sequentially applied to scanning electrode 21 to scanning electrode 2n, and thereby a character, an image or a like are displayed.
Further, the conventional display driving circuit of this example is a semiconductor integrated circuit of a CMOS (Complementary Metal Oxide Semiconductor) configuration mainly including a controller 7, a data electrode driving circuit 8 and a scanning electrode driving circuit 9.
The controller 7 generates a start pulse SP1 and a shift clock CK1 to be supplied to the data electrode driving circuit 8 and a start pulse SP2, a shift clock CK2 and an enable signal EN to be supplied to the scanning electrode driving circuit 9.
The data electrode driving circuit 8 is mainly provided with a shift register, a data register, a latch, a level shifter, a digital analog converter (DAC) and plural drivers (not shown).
The data electrode driving circuit 8 starts to take red data DR, green data DG, and blue data DB synchronously with the shift clock CK1 into the shift register based on the start pulse SP1, and then, takes output data from the shift register into the data register at a rising of the shift clock CK1. Then, the data electrode driving circuit 8 holds the output data temporarily in the latch, converts it into a predetermined voltage by the level shifter, converts the predetermined voltage into analog data red signal, analog data green signal and analog data blue signal by the DAC, applies amplification and buffer to these signals and sequentially applies them to a corresponding data electrode among data electrode 31 to data electrode 3m in the crystal panel 1 by the plural drivers.
The scanning electrode driving circuit 9, as shown in FIG. 8, is mainly provided with a shift register 10, NAND gate 111 to NAND gate 11n and driver 121 to driver 12n.
The shift register 10 is a serial-in parallel-out shift register including n-pieces of delay flip-flops (DFFS), executes a shift operation for shifting the start pulse SP2 synchronously with the shift clock CK2 based on a power supply voltage VCC and supplies each bit of n-bits of parallel data to each second input terminal of NAND gate 111 to NAND gate 11n. Each of NAND gate 111 to the NAND gate 11n inverts each bit of n-bits parallel data and supplies an inverted bit to a corresponding driver among driver 121 to driver 12n when each enable signal EN supplied from the controller 7 to each first input terminal is an xe2x80x9cHxe2x80x9d level. Each driver 121 to the driver 12n applies amplification and buffer to each bit of n-bits of parallel data inverted and supplied from a corresponding NAND gate (NAND gate 111 to NAND gate 11n) and sequentially applies it to a corresponding scanning electrode among scanning electrode 21 to scanning electrode 2n as n-pieces of scanning signals in the liquid crystal panel 1.
Next, explanations will be given of a part of an operation in the display driving circuit of the above-mentioned configuration. First, when a power supply is turned ON, the power supply voltage VCC is applied to the shift register 10 in the scanning electrode driving circuit 9.
In this case, in order to avoid latch-up in the scanning electrode driving circuit 9, the controller 7 applies a power-on-reset (not shown) so as to not output various control pulses until a constant time in which the power supply voltage VCC becomes stable passes after the power supply is turned ON.
Here, the latch-up is a phenomenon in which an electric current continuously flows from a power supply terminal to a ground terminal so long as the power supply voltage is lowered in a semiconductor integrated circuit of a CMOS configuration. Explanations will be given of reasons that the latch-up occurs in the scanning electrode driving circuit 9. Immediately after turning the power supply ON, output data from the shift register is irregular. When such irregular output data are directly supplied to driver 121 to driver 12n, in a worst case, namely, in a case in that all output data of the shift register 10 are different, an irregular over-current exceeding current supply capacities of driver 121 to driver 12n which is a current of several times of a capacity in a normal operation flows into all driver 121 to the driver 12n and a large voltage drop occurs, therefore, the latch-up occurs.
Then, after the constant time passes and power-on-reset is released, the controller 7 supplies the start pulse SP2 of one vertical synchronous period and the shift clock CK2 of one horizontal synchronous period to the shift register 10 and supplies an enable signal EN of an xe2x80x9cLxe2x80x9d level to each first input terminal of NAND gate 111 to NAND gate 11n. With this operation, the shift register 10 starts a normal shift operation, however, the enable signal is the xe2x80x9cLxe2x80x9d level, therefore, regardless of any state of each bit of n-bits of parallel data output NAND gate 111 to NAND gate 11n is kept at the xe2x80x9cHxe2x80x9d level.
Then, the shift register 10 starts the normal shift operation, after at least one vertical synchronous period in a display area of the liquid crystal display 1 passes, the controller 7 sets the enable signal EN to the xe2x80x9cHxe2x80x9d level. With this operation, it becomes possible for NAND gate 111 to NAND gate 11n to invert and output each bit of n-bits of parallel data supplied from the shift resister 10. Therefore, when a next start pulse SP2 is supplied from the controller 7, driver 121 to driver 12n apply amplification and buffer to each bit of n-bits of parallel data inverted and supplied from a corresponding NAND gate among NAND gate 111 to NAND gate 11n and sequentially apply to a corresponding scanning electrode among scanning electrode 21 to scanning electrode 2n in the liquid crystal panel 1 as n-pieces of scanning signals.
As above described, with this configuration of the example, output data of the shift register 10 are not transferred to each driver 121 to driver 12n until all irregular output data of the shift register 10 are erased immediately after releasing the power-on-reset of the controller 7. As a result, it is possible for driver 121 to driver 12n to prevent an irregular over-current from occurring and to keep a current of a normal value and it is possible to completely prevent a latch-up from occurring.
Now, in the above-mentioned conventional display driving circuit, during at least one vertical synchronous period in the display area of the liquid crystal panel 1 after the shift register starts a normal shift operation, a shift clock CK2 of one horizontal synchronous period is supplied to the shift register and thereby irregular output data of the shift register 10 immediately after turning the power supply ON are erased, so that the shift register 10 is initialized.
In such initialization of the shift register 10, there is a problem in that a character, an image and a like can be displayed on the liquid crystal panel 1 for a long time since no scanning signal is applied to each scanning electrode 21 to the scanning electrode 2n during at least one vertical synchronous period in the display area of the liquid crystal panel 1.
In view of the above, it is an object of the present invention to provide a display driving method and a display driving circuit capable of displaying a character, an image or a like immediately after turning a power supply ON.
According to a first aspect of the present invention, there is provided a display driving method for driving a display in which (nxc3x97m) pieces of pixels are arranged at intersection points of n-pieces of scanning electrodes at predetermined intervals in a row direction and m-pieces of signal electrodes at predetermined intervals in a column direction, where n of the n-pieces is a positive integer and m of the m-pieces is a positive integer, by applying each bit of n-bits of parallel data of a shift register for shifting a start pulse synchronously with a first shift clock of one horizontal synchronous period to the n-pieces of scanning electrodes and by applying m-pieces of data signals to the m-pieces of signal electrodes, the display driving method including:
a step of, after tuning a power supply ON, supplying a second shift clock of a period shorter than the one horizontal synchronous period to the shift register for n-periods at least instead of the first shift clock; and
a step of stopping each bit of output data from the shift register from transferring to n-pieces of drivers at least during a period corresponding to n-pieces of periods.
In the foregoing, a preferable mode is one wherein all of the n-pieces of drivers are in either an OFF voltage output state or an ON voltage output state by stopping transferring each bit of output data of the shift register to the n-pieces of drivers.
According to a second aspect of the present invention, there is provided a display driving method for driving a display in which (nxc3x97m) pieces of pixels are arranged at intersection points of n-pieces of scanning electrodes at predetermined intervals in a row direction and m-pieces of signal electrodes at predetermined intervals in a column direction, where n of the n-pieces is a positive integer and m of the m-pieces is a positive integer, by applying each corresponding bit of n-bits of parallel output data of each of two shift registers for shifting a same start pulse synchronously with a first shift clock of one horizontal synchronous period to both ends of a same scanning electrode among the n-pieces of scanning electrodes and by applying m-pieces of data signals to the m-pieces of signal electrodes, the display driving method including:
a step of, after turning a power supply ON, supplying a second shift clock of a period shorter than the one horizontal synchronous period to the two shift registers for n-periods at least instead of the first shift clock; and
a step of stopping each bit of output data from the two shift registers from transferring to each of the n-pieces of drivers at least during a period corresponding to the n-pieces of periods.
In the foregoing, a preferable mode is one wherein all of 2n-pieces of drivers are in either an OFF voltage output state or an ON voltage output state by stopping transferring each bit of output data of the two shift registers to each corresponding driver among the n-pieces of drivers.
Also, a preferable mode is one wherein a period of the second shift clock is 1 xcexcs.
Furthermore, a preferable mode is one wherein the display is a liquid crystal display or an EL panel.
According to a third aspect of the present invention, there is provided a display driving circuit for driving a display in which (nxc3x97m) pieces of pixels are arranged at intersection points of n-pieces of scanning electrodes at predetermined intervals in a row direction and m-pieces of signal electrodes at predetermined intervals in a column direction, where n of the n-pieces is a positive integer and m of the m-pieces is a positive integer, by applying each bit of n-bits of parallel data of a shift register for shifting a start pulse synchronously with a first shift clock of one horizontal synchronous period to the n-pieces of scanning electrodes and by applying m-pieces of data signals to the m-pieces of signal electrodes, the display driving circuit including:
a first shift clock generating circuit for generating a first shift clock of one horizontal synchronous period;
a second shift clock generating circuit for generating a second shift clock of a period shorter than the one horizontal synchronous period;
a shift register for shifting a start pulse synchronously with any one of the first shift clock and the second shift clock and outputting n-bits of parallel output data;
an enable signal generating circuit for generating an enable signal in a non-active state during a predetermined period equal to n-periods of the second shift clock at least after turning a power supply ON;
n-pieces of gate circuits for receiving n-bits of output data of the shift register, for outputting the n-bits of output data of the shift register when the enable signal is in the active state and for not outputting n-bits of output data of the shift register when the enable signal is in the non-active state;
n-pieces of drivers for applying amplification and buffer to each bit of output data of the shift register supplied through the n-pieces of gate circuits and for outputting the output data as n-pieces of scanning signals; and
a shift clock switching circuit for supplying the second shift clock to the shift register when the enable signal is in the non-active state and for supplying the first shift clock to the shift register after the predetermined period passes.
In the foregoing, a preferable mode is one wherein all of the n-pieces of drivers become any one of an OFF voltage output state and an ON voltage output state when the n-pieces of gate circuits do not output n-bits of output data of the shift register.
According to a fourth aspect of the present invention, there is provided a display driving circuit for driving a display in which (nxc3x97m) pieces of pixels are arranged at intersection points of n-pieces of scanning electrodes at predetermined intervals in a row direction and m-pieces of signal electrodes at predetermined intervals in a column direction, where n of the n-pieces is a positive integer and m of the m-pieces is a positive integer, by applying a corresponding scanning signal among n-pieces of scanning signals to both sides of a same scanning electrode among the n-pieces of scanning electrodes and by applying m-pieces of data signals to the m-pieces of signal electrodes, the display driving circuit including:
a first shift clock generating circuit for generating a first shift clock of one horizontal synchronous period;
a second shift clock generating circuit for generating a second shift clock of a period shorter than the one horizontal synchronous period;
a first shift register and a second shift register for shifting a start pulse synchronously with either the first shift clock or the second shift clock and for respectively outputting n-bits of parallel output data;
an enable signal generating circuit for generating an enable signal in a non-active state during a predetermined period corresponding to n-period of the second shift clock at least after turning a power supply ON;
2n-pieces of gate circuits, each of n-pieces of gate circuits provided for each of the first shift register and the second shift register for receiving each of n-bits of output data of a corresponding shift register in the first shift register and the second shift register, for outputting the n-bits of output data of the corresponding shift register when the enable signal is in the active state and for not outputting n-bits of output data of the corresponding shift register when the enable signal is in the non-active state;
2n-pieces of drivers correspondingly provided for the 2n-pieces of gate circuits and for applying amplification and buffer to a corresponding bit of output data of the corresponding shift register supplied through a corresponding gate circuit among the n-pieces of gate circuits and for outputing the corresponding bit as a corresponding scanning signal; and
a shift clock switching circuit for supplying the second shift clock to the first shift register and the second shift register at a same time when the enable signal is in the non-active state and for supplying the first shift clock to the first shift register and the second shift register after the predetermined period passes.
In the foregoing, a preferable mode is one wherein all of the 2n-pieces of drivers become either a OFF voltage output state or an ON voltage output state when the corresponding gate circuit does not output a corresponding bit of output data of the corresponding shift register.
Also, a preferable mode is one wherein the enable signal generating circuit includes:
a clear circuit for waveform shaping a rising edge of a power supply voltage when a power supply is turned ON;
an AND gate for outputting a logic multiplication of the clear signal and the enable signal as a counter enable signal;
a counter cleared when the clear signal rises, for becoming possible to operate by the counter enable signal, for counting up at a rising of the second shift clock and for outputting count data; and
a comparator cleared when the clear signal rises, for comparing the count data with setting data corresponding to the predetermined period which is previously set and for outputting the enable signal when the count data agrees with the setting data.
Also, a preferable mode is one wherein the gate circuit is any one of a NOR gate, a NAND gate and a three state buffer.
Also, a preferable mode is one wherein a period of the shift clock is 1 xcexcs.
Furthermore, a preferable mode is one wherein the display is a liquid crystal display or an EL panel.
With above-mentioned configurations, it is possible to display a character, an image or a like immediately after turning a power supply ON.
Also, after turning a power supply ON, a second shift clock of a period shorter than the one horizontal synchronous period is supplied to the shift register during n-periods at least instead of the first shift clock and each bit of output data from the shift register is stopped from transferring to n-pieces of drivers at least during a period corresponding to n-pieces of periods. As a result, it is possible to prevent an unstable over-current of n-pieces of drivers from occurring so as to set a current of a normal value and to prevent a latch-up from occurring. Also, it is possible to display the character, the image or the like immediately after tuning a power supply ON.
Also, with this configuration, after turning a power supply ON, a second shift clock of a period shorter than the one horizontal synchronous period is supplied to the shift register during n-periods at least instead of the first shift clock and each bit of output data from the shift register is stopped from transferring to the n-pieces of drivers at least during a period corresponding to the n-pieces of periods. As a result, in spite of a large screen, it is possible to prevent an unstable over-current of n-pieces of drivers from occurring so as to set a current of a normal value and to prevent a latch-up from occurring. Also, it is possible to display the character, the image or the like immediately after turning a power supply ON